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Full changelogEngine 1.26.4

Trace Inductance & di/dt

PCB & Copper

Trace inductance, with or without a return plane, and the L·dI/dt voltage when the current steps.

Inputs

Board profile

Fills Copper weight and Dielectric constant from your board profile.

A
Allowed movement of the rail or reference during the edge
Copper weight and frequency
Hz
100 MHz

Results

1 passed
Inductance L
1.747nH
Pass

Checked: L ≤ 2.5 nH, which keeps 200 mA in 5 ns within the 100 mV budget
Inductive kick VL
69.88mV
Per millimetre
0.35nH/mm
All results (2)
Reactance XL

at 100 MHz
1.098Ω
Copper cross-section
8700µm²
L ΔI / tr for 200 mA in 5 ns

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Geometry

The principle

On a board, inductance, not resistance, decides whether a rail holds still when a load switches. The spike is L·dI/dt, so a few nanohenries and a fast edge give hundreds of millivolts. Where the return current flows matters more than the trace itself.

Isolated conductor (partial self-inductance)
L=μ0 l2π[ln⁡2lw+t+12+0.2235 w+tl]L = \frac{\mu_0\, l}{2\pi}\left[\ln\frac{2l}{w+t} + \frac{1}{2} + 0.2235\,\frac{w+t}{l}\right]
Rosa, as tabulated by Grover. Valid for l much greater than w + t. The return is infinitely far away, so this is an upper bound.
Over a return plane (loop inductance)
L=Z0εeffc  lL = \frac{Z_0\sqrt{\varepsilon_{eff}}}{c}\; l
From the line's impedance and delay, with Z0 and εeff from the Hammerstad-Jensen microstrip model.
The spike
VL=L ΔItrV_L = L\,\frac{\Delta I}{t_r}
Reactance
XL=2πfLX_L = 2\pi f L
  • lltrace length
  • w,tw, ttrace width and copper thickness
  • hhheight of the trace above the return plane
  • Z0,εeffZ_0, ε_effcharacteristic impedance and effective permittivity of the trace as a microstrip
  • ΔIΔIthe current step
  • trt_rthe time the step takes
  • μ0μ₀permeability of free space
More detail

About 1 nH/mm is a fair estimate for a wire or an isolated trace. Over a plane on a four-layer stack it is nearer 0.3 nH/mm, and lower still for a wide pour over thin dielectric.

Decoupling is a loop, not a capacitor. Put the capacitor's via next to its pad and the pin's via next to the pin, and let the planes carry the current between them. Every millimetre of trace in that loop adds inductance.

Ground bounce is the same L·dI/dt on a shared return when many outputs switch together. Use a short, plane-backed return and fewer outputs per return pin.

20 mm of isolated 0.25 mm trace, 1 oz
w + t = 0.285 mm, so L = 2 × 10⁻⁷ × 0.02 × [ln(140) + 0.5 + 0.003] = 21.8 nH, about 1.1 nH/mm. A 0.2 A step in 5 ns across it gives 0.87 V.
5 mm of the same trace 0.2 mm above a plane
The microstrip is close to 55 Ω with ε_eff near 3.1, so L per length is 55 × 1.76 / c ≈ 0.32 nH/mm and the 5 mm run is 1.6 nH: the same step gives 65 mV.
References: Rosa, E. B., The Self and Mutual Inductances of Linear Conductors, Bulletin of the Bureau of Standards. Grover, F. W., Inductance Calculations. Hammerstad and Jensen, for the microstrip case. Johnson and Graham, High-Speed Digital Design, on ground bounce and decoupling loops. Related: Decoupling & Bulk Capacitance, Controlled Impedance & Delay.

Engine version ⁨1.26.4⁩