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Full changelogEngine 1.26.4

Voltage Divider

Analog & Interfacing

Output of a two-resistor divider, or the pair for a target, with loading and tolerance.

Inputs

V
Ω
10 kΩ
Ω
3.3 kΩ
V
Keep it well above the bias current of the pin it feeds.
A
Load
Ω

Results

Output (unloaded) Vout
2.9774V
Show working
  1. Unloaded outputV_out = V_in × R₂ / (R₁ + R₂) = 12 V × 3.3 kΩ / (10 kΩ + 3.3 kΩ) = 2.9774 V
  2. Divider currentI_div = V_in / (R₁ + R₂) = 12 V / 13.3 kΩ = 902.3 µA
  3. Thévenin source resistanceR_th = R₁ ∥ R₂ = 10 kΩ × 3.3 kΩ / (10 kΩ + 3.3 kΩ) = 2.481 kΩ
Divider current Idiv
902.3µA
Tolerance spread (worst case)
All results (2)
Thévenin source R Rth
2.481kΩ
Total dissipation P

R₁ 8.141 mW · R₂ 2.686 mW
10.83mW
Detail
QuantityValue
R₁ / R₂ ratio3.0303
Attenuation
Worst-case output
Vin ripple at the output
Error per 1 nA of input bias current
Vout vs load

Accuracy

Verified against

2 independent cases. See the working.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Parts that track move together.Inputs in the same group move together, like the parts of a matched network. Leave independent parts ungrouped: that is the safe choice.

Circuit

The principle

The same current flows through R₁ and R₂, so the input voltage splits in proportion to the resistances. The output holds that value only while the load draws little current, so the Thévenin resistance matters as much as the ratio.

Unloaded output
Vout=Vin R2R1+R2V_{out} = V_{in}\,\frac{R_2}{R_1 + R_2}
Thévenin equivalent seen by the next stage
Vth=VoutRth=R1∥R2=R1R2R1+R2V_{th} = V_{out} \qquad R_{th} = R_1 \parallel R_2 = \frac{R_1 R_2}{R_1 + R_2}
The next stage sees a source Vth behind a resistance Rth.
Loaded output
Vout L=Vin R2∥RLR1+(R2∥RL)V_{out}^{\,L} = V_{in}\,\frac{R_2 \parallel R_L}{R_1 + (R_2 \parallel R_L)}
Tolerance sensitivity
ΔVoutVout=R1R1+R2 (δ2−δ1)=(1−VoutVin)(δ2−δ1)\frac{\Delta V_{out}}{V_{out}} = \frac{R_1}{R_1+R_2}\,(\delta_2 - \delta_1) = \left(1-\frac{V_{out}}{V_{in}}\right)(\delta_2-\delta_1)
First order. Worst case |δ₂−δ₁| = 2·tol; typical (RSS) √2·tol. The worst case shown is exact: R₁ at one limit and R₂ at the other.
Design from a current budget
R1+R2=VinIdivR2=(R1+R2)VoutVinR_1 + R_2 = \frac{V_{in}}{I_{div}} \qquad R_2 = (R_1+R_2)\frac{V_{out}}{V_{in}}
  • VinV_{in}input voltage
  • R1R_1top resistor, input to output
  • R2R_2bottom resistor, output to ground
  • RLR_Lload on the output
  • RthR_{th}output (Thévenin) resistance
  • IdivI_{div}current through the divider
  • δ1,2\delta_{1,2}fractional error of each resistor
More detail

The loading rule

RL ≥ 10 · Rth keeps the loading error under about 10 %; RL ≥ 100 · Rth keeps it under 1 %. If you cannot meet that, buffer the output with an op-amp follower.
Related: Preferred-Value Synthesiser for ratio matching, ADC Resolution & Noise Budget for settling into an ADC.

Engine version ⁨1.26.4⁩