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Full changelogEngine 1.26.4

Line Termination & Reflections

Signal & Timing

Does this line need termination, and what does each scheme cost?

Inputs

From Controlled Impedance.
Ω
Driver datasheet or IBIS model.
s
1 ns
IBIS model, or the output V–I curve in the driver datasheet.
Ω
The driver's supply, for CMOS.
V
Absolute maximum ratings, receiver datasheet.
V
Line delay, load and limits
About 6 on an outer FR-4 layer, 7 on an inner one. From Controlled Impedance (propagation delay). 3.3356 ps/mm is the speed of light; nothing is faster.
Blank for a CMOS input.
Ω
Absolute maximum ratings, receiver datasheet.
V
Driver datasheet, output current at valid logic levels.
A
12 mA
Resistor power
A clock's frequency; for data, half the bit rate.
Hz
50 MHz
Resistor datasheet; 0603 thick film is often 0.1 W.
W
From the derating curve at your ambient, and your own policy.
%

Results

Peak at the receiver Vpeak

overshoot 0.0 %; DC levels 0 V and 3.3 V
3.3V
Pass

Checked: peak ≤ your 3.6 V Vabs (receiver datasheet), and overshoot ≤ 10 %, failing past 20 % (design margin): 0.0 % here, receiver open
Show working
  1. One-way delayt_d = t_pd × l = 5.96 ps/mm × 100 mm = 596 ps
  2. Series resistorR_s = Z₀ − R_out = 50 − 10 = 40 Ω
  3. Source reflectionΓ_s = (R_src − Z₀) / (R_src + Z₀) = (50 − 50) / (50 + 50) = 0
  4. Launched stepV_launch = V × Z₀ / (Z₀ + R_src) = 3.3 × 50 / (50 + 50) = 1.65 V
  5. Peak at the receiverV_peak = V_lo + V_launch × (1 + Γ_L) = 0 + 1.65 × (1 + 1) = 3.3 V, overshoot 0.0 %
Termination 

Rs, nearest E96 40.2 Ω
40Ω at the driver
Lowest at the receiver Vlow

on the falling edge
0V
Driver DC current Idc

the larger of the high and the low state
0A
All results (4)
Resistor power PR

an upper bound: Rs's share of the energy lost charging the line, twice a cycle, with instant edges
5.192mW
One-way delay td
596ps
Critical length (conservative) lcons

hard limit 83.9 mm
28mm
Settling to ±5 % ts

from the start of the driver's edge, to Vhi ± 5 % of the step
1.55ns
Arrivals at the receiver, at each ramp's end
ArrivalTimeReceiver voltage
11.596 ns3.3 V
Rising edgeFalling edge

Accuracy

Source
  • Johnson and Graham

Johnson and Graham, High-Speed Digital Design the equation

Checked against: The datasheets of your parts: the driver's output resistance (or IBIS model) and current rating, the receiver's absolute maximum input range, and the resistor's power rating

Precision
Exact for a lossless line with resistive ends, summing every reflection until it is below 10⁻⁷ of the swing.

Each arrival is drawn as a full linear ramp of length t_r, slightly faster than the 10–90 % edge it stands for, so the peak errs high. AC termination takes the capacitor as a short during the edge, which line simulations support inside its validity limits. The driver's output resistance usually moves the answer most: take it from the IBIS model.

Most of the uncertainty comes from Driver output resistance. Tighten that first.

Verified against

3 independent cases. See the working.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Parts that track move together.Inputs in the same group move together, like the parts of a matched network. Leave independent parts ungrouped: that is the safe choice.

Circuit

The principle

A trace is a transmission line once its round trip is comparable with the edge. The step the driver launches travels to the receiver, and wherever the resistance at an end differs from Z0, part of it reflects. A CMOS input is nearly open and reflects almost all of it, and a low-resistance driver sends most of that back again, so the receiver rings above its supply and below ground. A termination matches one end to the line, so the first reflection is absorbed there. This page sums the reflections for each scheme and checks the peak, the lowest level, the driver's DC current and the resistor's power.

Reflection
Γ=R−Z0R+Z0\Gamma = \frac{R - Z_0}{R + Z_0}
At the driver R = Rsrc, giving Γs. At the receiver R is the far end during the edge, giving ΓL: 1 for an open end, and R ∥ RL for AC, with the capacitor taken as a short.
Launch
Vlaunch=V Z0Z0+RsrcV_{launch} = V\,\frac{Z_0}{Z_0 + R_{src}}
The driver and the line form a divider: the line looks like Z₀ until the first reflection returns.
Receiver
Vrx=Vlo+Vlaunch (1+ΓL)∑n(ΓLΓs)n,arrival n at (2n+1) tdV_{rx} = V_{lo} + V_{launch}\,(1 + \Gamma_L)\sum_{n} (\Gamma_L \Gamma_s)^{n}, \qquad \t{arrival } n \t{ at } (2n + 1)\,t_d
Each arrival is a linear ramp of length tr, slightly faster than the 10–90 % edge it stands for, so the peak errs high. Summed until an arrival is below 10⁻⁷ of the swing, at most 2 000 arrivals. Exact for a lossless line with resistive ends.
Critical length
lcrit=tr2 tpdlcons=tr6 tpdl_{crit} = \frac{t_r}{2\,t_{pd}} \qquad l_{cons} = \frac{t_r}{6\,t_{pd}}
As on Controlled Impedance: above lcrit the round trip is longer than the edge. Below lcons the line can be treated as a lumped connection.
Termination values
Rs=Z0−RoutRp=Z0R1∥R2=Z0R C≥3⋅2 tdR_s = Z_0 - R_{out} \qquad R_p = Z_0 \qquad R_1 \parallel R_2 = Z_0 \qquad R\,C \geq 3 \cdot 2\,t_d
Thevenin: R₁ = Z₀V/Vtt to the swing and R₂ = Z₀V/(V − Vtt) to ground, so the line idles at Vtt. AC: R = Z₀, and C is rounded up in E12. The 3 is a design margin.
AC power
P=C V2ftanh⁡14fRCP = C\,V^{2} f \tanh\frac{1}{4 f R C}
The periodic steady state of a 0-to-V square wave into R and C. Series is an upper bound, (Rs/Z₀)(td/Z₀)V²f: Rs's share of the energy lost charging the line, twice a cycle, with instant edges. Parallel and Thevenin take the worst static level.
Driver DC current
I=max⁡(∣V−Vhi∣,  ∣Vlo∣)RsrcI = \frac{\max\left(|V - V_{hi}|,\; |V_{lo}|\right)}{R_{src}}
Vhi and Vlo are the receiver's DC levels with the driver high and low.
  • Z0Z_0line impedance
  • RoutR_{out}driver output resistance
  • RsrcR_{src}resistance at the driver end, Rout + Rs
  • RLR_Lreceiver load; open when blank
  • Rs, Rp, R1, R2R_s,\,R_p,\,R_1,\,R_2series, parallel and Thevenin termination resistors
  • R, CR,\,CAC termination resistor and capacitor
  • Γs, ΓL\Gamma_s,\,\Gamma_Lreflection coefficients at the driver and at the receiver
  • tdt_done-way delay, tpd × l
  • tpdt_{pd}delay per length
  • trt_rrise time, 10–90 %
  • llline length
  • VVdriver swing
  • VttV_{tt}Thevenin level
  • Vhi, VloV_{hi},\,V_{lo}receiver DC levels, driver high and low
  • fftoggle frequency
More detail

Choosing a scheme

  • Series at the driver draws no DC current. The receiver sees the full step at the far end, but a load part-way along sees half of it until the reflection returns, so it suits one receiver at the end.
  • Parallel to ground absorbs the wave at the receiver, but draws DC current in the high state and lowers the high level.
  • Thevenin sets the line's idle level at Vtt, so the driver sources current in one state and sinks it in the other. With Vtt at half the swing, its worst current is about half that of parallel to ground. The divider draws supply current all the time.
  • AC blocks the DC current with its capacitor, and pays in power at every edge instead.

Not modelled

The line is lossless and the receiver's input capacitance is left out. The peak is for one edge on a settled line: a pattern faster than the settling time can stack reflections. AC takes the capacitor as a short during the edge. Line simulations support this for R·C ≥ 3tr and Rout ≥ 0.2Z0 (td 0.1 to 3 ns, tr 0.1 to 2 ns, f 1 to 200 MHz).

Terminate a line longer than its conservative critical length, or check it here.
References: H. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall. Related: Controlled Impedance & Delay, for tpd and the critical length.

Engine version ⁨1.26.4⁩