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UART Baud Error & Timer Prescaler

Signal & Timing

Will this clock talk to that device, and which prescaler gives this timer frequency?

Inputs

The clock into the USART: fOSC on an AVR, the APB clock on an STM32 (datasheet clock tree).
Hz
16 MHz
b/s
Crystal or oscillator datasheet: tens of ppm for a crystal; an internal RC oscillator is often 1 % (10 000 ppm) or more.
ppm
The other device's total baud error, from its datasheet or this page.
%
Receiver limit
Blank: 2.0 % at 16 samples per bit, 1.5 % at 8 (the ATmega328P datasheet, 8 data + parity bits). For another part, its receiver tolerance from its datasheet or reference manual: the total both ends may use.
%
8 for 8N1, 9 for 8E1.

Results

Total link error
1.085%
Pass

Checked: total ≤ L = 2.0 % (the AVR figure, ATmega328P datasheet, D = 8), failing past 3.0 % (1.5 × L, design margin): 1.085 % here
Show working
  1. Ideal dividerx = f_CK / (16 × baud) = 16 MHz / (16 × 115 200) = 8.681 → mantissa 8, fraction 11, BRR = 0x8B
  2. Actual baud ratebaud = f_CK / (16 × (mantissa + fraction / 16)) = 16 MHz / (16 × (8 + 11 / 16)) = 115.108 kb/s
  3. Baud error at this ende = baud_actual / baud − 1 = 115108 / 115 200 − 1 = −0.07994 %
  4. Total link error|e| + tol + remote = 0.07994 % + 0.005 % + 1 % = 1.085 %
Actual baud rate 

this end −0.07994 % from 115 200 b/s
115.108kb/s
Baud error at this end e
−0.07994%
Register 

mantissa 8, fraction 11
BRR = 0x8B
All results (3)
Limit used L

the AVR figure, ATmega328P datasheet, D = 8
2.0%
Nearest exact clocks 

whole multiples of 115 200 b/s
15.8976MHz and 16.0128 MHz
Ideal divider x

fCK / (16 × baud), before rounding to sixteenths
8.68056

Accuracy

Source
  • Microchip (Atmel) ATmega328P datasheet: USART baud rate register settings
  • STMicroelectronics STM32F1 reference manual (RM0008): USART fractional baud rate generation

Microchip (Atmel) ATmega328P datasheet: USART baud rate register settings the equation

STMicroelectronics STM32F1 reference manual (RM0008): USART fractional baud rate generation, and the TIMx_PSC and TIMx_ARR registers the equation

Checked against: Microchip (Atmel) ATmega328P datasheet: asynchronous operational range and recommended maximum receiver error

Precision
Exact integer arithmetic for the divider and timer registers.

The link total is a first-order sum of this end's error, its clock tolerance and the far end's error. Held against the datasheet's default, one end's share of the receiver's range, it is conservative. Of the inputs, the far end's error is usually the least known.

Verified against

3 independent cases. See the working.

This is a design aid. The engineer remains responsible for the design and for checking the standard itself.

Parameter sweep

Vary one input over a range and see the answer and verdict at each step, as a table and a curve.Pro

Worst-case corners

Put a tolerance on each input and get the worst-case band around the answer.Pro

Give at least one input a tolerance above zero.

Waveform

The principle

A UART receiver times each bit from the falling edge of the start bit and samples it near the middle. When the two ends run at different rates, the sample point slips a little each bit, and by the last bit of the frame it can miss. Each end makes its rate by dividing a clock, with an integer divider or one with a 1/16 fraction, so most clocks cannot hit a standard rate exactly. This page works out the divider and the error it leaves, adds the clock tolerance and the far end's error, and checks the total against the receiver's limit. In timer mode it finds the prescaler and auto-reload values that come nearest a target frequency.

Integer divider (AVR)
baud=fOSC16 (UBRR+1)baud=fOSC8 (UBRR+1)    with U2X\t{baud} = \frac{f_{OSC}}{16\,(UBRR + 1)} \qquad \t{baud} = \frac{f_{OSC}}{8\,(UBRR + 1)} \;\; \t{with U2X}
ATmega328P datasheet. UBRR is the nearest whole divider less one, from 0 to 4095 (12 bits).
Fractional divider (STM32)
baud=fCK16⋅USARTDIV,USARTDIV=mantissa+fraction16\t{baud} = \frac{f_{CK}}{16 \cdot USARTDIV}, \qquad USARTDIV = \t{mantissa} + \frac{\t{fraction}}{16}
STM32F1 reference manual. The fraction is rounded to sixteenths. One that rounds to 16 carries into the mantissa: ST's own worked example takes USARTDIV 50.99 to BRR 0x330. BRR = 16 × mantissa + fraction, and the mantissa has 12 bits.
Baud error
e=baudactualbaud−1e = \frac{\t{baud}_{actual}}{\t{baud}} - 1
Link check
∣e∣+tol+eremote≤L|e| + \t{tol} + e_{remote} \leq L
A first-order sum. The datasheet's recommended figure assumes the two ends share the error equally, so comparing both ends' sum with it is a conservative design margin. Check up to 1.5 × L, then fail (design margin).
Receiver range (ATmega328P datasheet)
Rslow=(D+1) SS−1+D S+SFRfast=(D+2) S(D+1) S+SMR_{slow} = \frac{(D + 1)\,S}{S - 1 + D\,S + S_F} \qquad R_{fast} = \frac{(D + 2)\,S}{(D + 1)\,S + S_M}
The slowest and fastest incoming rates the receiver accepts, as ratios to its own. The datasheet gives them for D = 5 to 10, with a recommended maximum receiver error: for D = 8, ±2.0 % at normal speed and ±1.5 % with U2X. Those two are the default L.
Timer
f=fclk(PSC+1)(ARR+1)f = \frac{f_{clk}}{(PSC + 1)(ARR + 1)}
STM32F1 reference manual, TIMxPSC and TIMxARR, counting up: the counter steps at fclk/(PSC + 1) and overflows every ARR + 1 steps. ARR ≥ 1: the counter stops while ARR is 0. When N = fclk/ftarget factors within the register widths, the exact pair with the largest ARR is taken; otherwise the pair with the least error, the larger ARR on a tie.
Drift
Δt=tol×86 400  s per day\Delta t = \t{tol} \times 86\,400 \; \t{s per day}
How far a timebase from this clock can wander in a day at its full tolerance.
  • fOSC, fCKf_{OSC},\,f_{CK}the USART clock
  • UBRR, USARTDIVUBRR,\,USARTDIVthe divider: AVR UBRR, and the STM32 divider held in BRR
  • baud\t{baud}the baud rate wanted
  • eethis end's baud error
  • tol\t{tol}clock tolerance
  • eremotee_{remote}the far end's total error
  • LLthe allowed total error
  • DDdata + parity bits in a frame
  • D0…D7D_0 \ldots D_7the data bits, least significant first
  • tbitt_{bit}one bit time, 1/baud
  • SSsamples per bit: 16, or 8 with U2X
  • SF, SMS_F,\,S_Mthe first and middle majority samples: 8 and 9 at 16 samples, 4 and 5 at 8
  • fclkf_{clk}the timer clock, into its prescaler
  • PSC, ARRPSC,\,ARRprescaler and auto-reload register values
  • PSC+1PSC + 1clock cycles per counter step
  • ARR+1ARR + 1counter steps per period
  • f, Tf,\,Tthe timer frequency, and its period 1/f
More detail

Where the error goes

The receiver allows a total mismatch between the two rates, and both ends spend it: each one's divider error, and each one's clock tolerance. A crystal holds tens of ppm, which hardly counts; an internal RC oscillator is often 1 % or more, which can take the whole allowance. Longer frames leave less: Rslow and Rfast close in on 1 as data and parity bits are added.

Clocks that divide exactly

With an integer divider, a clock that is a whole multiple of 16 × the baud rate (8 × with U2X) gives no divider error. A fractional divider needs only a whole multiple of the baud rate. The page gives the two such clocks nearest yours.

Timer resolution

Of the pairs that give the same frequency, the largest ARR gives the finest PWM duty steps, 1/(ARR + 1) of the period.

Check both ends. A receiver that is well inside its own limit still fails when the far end spends the rest.
References: Microchip (Atmel) ATmega328P datasheet: the baud rate equations and the asynchronous operational range. STMicroelectronics STM32 reference manuals: USART fractional baud rate generation, and the TIMx_PSC and TIMx_ARR registers. Related: Crystal Load Capacitance, for the crystal's own ppm error.

Engine version ⁨1.26.4⁩