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سجل التغييرات الكاملالمحرّك 1.26.4

PDN Target Impedance

Power & Regulators

Impedance of a real capacitor bank against its target, and the frequency above which more capacitors stop helping.

هذه الصفحة غير مترجمة بالكامل بعد. الأجزاء غير المترجمة معروضة بالإنجليزية.

المدخلات

ملف اللوحة

Fills Dielectric constant between the planes from your board profile.

V
%
A
Hz
1 MHz
Pad, vias and loop to the plane, excluding the part's ESL
H
800 pH
H
2 nH
From the part's DC-bias curve at your rail voltage; small cases can lose over half
%
Via pair
Plane pair
Regulator
Ω
2 mΩ
H
2 µH
Hz
50 kHz
GroupCountC (F)ESR (Ω)Part ESL (H)Distance to load (m)
100 nF20 mΩ600 pH3 mm
4.7 µF8 mΩ1 nH12 mm
100 µF10 mΩ2.5 nH30 mm

النتائج

1 ناجحة · 1 للمراجعة
Peak impedance in band |Z|pk
104.2mΩ
ناجح

المعيار: peak |Z| ≤ Ztarget = 165 mΩ from 50 kHz (the loop bandwidth) to 72.29 MHz, at the worst-case 2 nH mounting inductance
Impedance at the stated frequency |Z|(f)

at 1 MHz
5.328mΩ
Highest frequency the board holds the target fmax
206.2MHz
Target impedance Ztarget
165mΩ
كل النتائج (6)
High-frequency inductance floor Lnode
First plane cavity mode fcav
Plane pair capacitance Cpl
1.904nF
Spreading inductance of the nearest group Lspread
Peak impedance at the typical mounting inductance
Two-via loop inductance, lower bound
Each group as the plane sees it
GroupCountC after deratingGroup ESRGroup LSpreading LBranch resonance
Local 0402 100 nF201.2 µF1 mΩ190 pH10.5 MHz
Mid 0805 4.7 µF822.6 µF1 mΩ463 pH1.56 MHz
Bulk 100 µF polymer2120 µF5 mΩ2.36 nH299 kHz
Diminishing returns on the first group
Count in the first groupPeak |Z|f_max
20
40
80
160
→ ∞
bank, worst-case mountbank, typical mountLocal 0402 100 nFMid 0805 4.7 µFBulk 100 µF polymer

إلى أي حد نعرف هذا الرقم

من أين تأتي الطريقة
  • Smith et al.
  • Smith and Bogatin

Smith, Anderson, Forehand, Pelc and Roy, Power distribution system design methodology and capacitor selection for modern CMOS technology, IEEE Transactions on Advanced Packaging المعادلة

Smith and Bogatin, Principles of Power Integrity for PDN Design Simplified المعادلة

صادقة ضمن
  • Plane pair separation 0.005 mm to 2 mm

Plane pair separation The spreading-inductance formula assumes the plane separation is much smaller than the distance from each group to the load. Outside this range it does not apply.

مدى دقتها
A lumped network with exact arithmetic, so the error lies in the inductances you enter.

Mounting inductance spans roughly 0.3 to 2 nH for ordinary pads and vias and sets the answer above about 30 MHz, so the verdict uses the worst-case value.

عملياً يهيمن على عدم اليقين مدخل واحد: Typical mounting inductance per part. ضيّقه يضِق معه الجواب.

يُقاس مقابل

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المقطع العرضي

المبدأ

A power distribution network is judged by its impedance seen from the load, across frequency, against a target: the allowed rail deviation divided by the current step. Each capacitor group sits behind its own mounting and spreading inductance. Between any two groups there is an anti-resonance that more of the same part will not remove.

Target impedance
Ztarget=VDD rΔIZ_{target} = \frac{V_{DD}\,r}{\Delta I}
One real capacitor
Zc(f)=Resr+j(2πfLc−12πfC),Lc=ESL+LmountZ_c(f) = R_{esr} + j\left(2\pi f L_c - \frac{1}{2\pi f C}\right), \qquad L_c = ESL + L_{mount}
N identical parts, inside one group only
Zg(f)=ResrN+j(2πfLcN−12πfNC)Z_g(f) = \frac{R_{esr}}{N} + j\left(\frac{2\pi f L_c}{N} - \frac{1}{2\pi f N C}\right)
Spreading inductance to a group at distance d
Lspread=μ0h2πln⁡drvL_{spread} = \frac{\mu_0 h}{2\pi}\ln\frac{d}{r_v}
The radial parallel-plate result. Valid while h is much smaller than d, and below the first cavity mode.
Plane pair capacitance
Cpl=ε0εrAhC_{pl} = \frac{\varepsilon_0 \varepsilon_r A}{h}
The node impedance
1Zpdn(f)=1Zvrm+∑i1Zg,i+j2πfLspread,i+j2πfCpl\frac{1}{Z_{pdn}(f)} = \frac{1}{Z_{vrm}} + \sum_i \frac{1}{Z_{g,i} + j 2\pi f L_{spread,i}} + j 2\pi f C_{pl}
The floor, and the frequency it imposes
Lnode=(∑i1Lc,i/Ni+Lspread,i)−1,fmax=Ztarget2πLnodeL_{node} = \left(\sum_i \frac{1}{L_{c,i}/N_i + L_{spread,i}}\right)^{-1}, \qquad f_{max} = \frac{Z_{target}}{2\pi L_{node}}
First plane cavity mode
fcav≈c02aεrf_{cav} \approx \frac{c_0}{2 a \sqrt{\varepsilon_r}}
  • ZtargetZ_{target}the impedance the rail deviation and the current step allow
  • LmountL_{mount}pad, via pair and the loop back to the plane, per part
  • LspreadL_{spread}inductance of the radial path from a group to the load
  • LnodeL_{node}all the branch inductances in parallel: the high-frequency floor
  • fmaxf_{max}the frequency at which that floor reaches the target
  • fcavf_{cav}first plane cavity mode; the lumped model does not apply above it
  • CplC_{pl}capacitance of the plane pair itself
  • rvr_vvia barrel radius, the inner limit of the radial spread
تفاصيل إضافية

When to stop adding capacitors

A 5 mΩ target with a 50 pH floor gives fmax = 15.9 MHz. Above fmax, only package and on-die capacitance help. The diminishing-returns table shows where more parts stop paying.

N in parallel applies only within a group

N parts divide R and L and multiply C only when they share a mount and a distance. Groups at different distances see different spreading inductance, which is why an anti-resonance appears between them.

Not modelled

Mutual inductance between adjacent mounts, and ESR change with frequency and temperature. DC-bias derating is the factor you enter from the part's own curve.

The plane pair appears as both a capacitance and a spreading inductance, which holds only well below the first cavity mode. Confirm with a two-port shunt-through VNA measurement; where it disagrees, trust the measurement.
Method: target impedance from Smith, Anderson, Forehand, Pelc and Roy; spreading and plane results after Smith and Bogatin.

إصدار المحرك ⁨1.26.4⁩